1. Technical Field
The present invention relates to a primitive cell, and more particularly, to a primitive cell having a gate pattern that is robust against electrostatic discharge (ESD).
2. Discussion of the Related Art
ESD is an electric current driven by an excess electric charge typically stored on an insulating object of a chip. Because chips are made from semiconductor materials such as silicon and insulating materials such as silicon dioxide, which can break down if exposed to ESD, precautions have been developed to guard against ESD.
For example, when an ESD stress is applied to a chip, an ESD protection circuit bypasses most of the ESD stress. However, the ESD protection circuit may not be 100 percent effective. As a result, damage may occur in an internal circuit of the chip, and when damage does occur, it is difficult to determine the location and extent of the damage.
FIG. 1 illustrates the layout of a primitive cell 100 implemented by a high finger gate transistor.
Referring to FIG. 1, the primitive cell 100 includes a PMOS transistor including an active region 130 that is formed inside a well 110 and a portion of a gate pattern 160 formed on the active region 130, and an NMOS transistor including an active region 150 that is formed on a substrate (not shown) and a portion of the gate pattern 160 formed on the active region 150. An electrically stable bias voltage from a high voltage source is applied to the well 110 via an active region 120, and an electrically stable bias voltage from a low voltage source or a ground voltage is applied to the substrate via an active region 140.
Although not illustrated in FIG. 1, a portion of the active region 130 separated by the gate pattern 160 is supplied with a high power source voltage and a portion of the active region 150 separated by the gate pattern 160 is supplied with a low power source voltage. The remaining portions of the active region 130 and the active region 150 are connected to each other to form an output terminal of an inverter.
Referring to FIG. 1, the PMOS transistor and the NMOS transistor form a finger gate transistor whose gates are spread like fingers to maximize the use of a predetermined active region and to increase the ratio of the width to the length of the gates of the finger gate transistor. The finger gate transistor is designed such that there are more finger gates in the PMOS transistor than in the NMOS transistor. This is due to the difference between the mobility of electrons and holes in the PMOS transistor and the NMOS transistor.
In the PMOS transistor and the NMOS transistor, ESD inducing components that accumulate in a common section thereof may adversely affect the gates of the PMOS and NMOS transistors.
For example, when a low power source is applied to the gates of the PMOS transistor and the NMOS transistor, the PMOS transistor is turned on and the NMOS transistor is turned off. Since the PMOS transistor and the NMOS transistor have high finger gates having many fingers with narrow widths and short lengths, the finger gates tend not to be robust against an applied ESD stress. Thus, the ESD components accumulated in a drain of a high finger NMOS transistor may cause damage to a weak finger gate of the NMOS transistor.
Further, even if a difference in the robustness of the multi-finger gates of the PMOS and the NMOS transistors against ESD is small, the finger gate of the NMOS transistor damaged by the ESD may still be destroyed. As such a need exists for a gate pattern for a primitive cell that is robust against ESD.